The VESA Local Bus is a local bus defined by the Video Electronics Standards Association, mostly used in personal computers based on the Intel 80486 CPU. VESA Local Bus worked alongside the ISA bus; it acted as a high-speed conduit for memory-mapped I/O and DMA, while the ISA bus handled interrupts and port-mapped I/O.
The VESA Local Bus was designed as a stop-gap solution to the problem of the ISA buss limited bandwidth. VESA had several flaws that served to limit its useful life substantially: 80486 dependence. The VESA Local Bus relied heavily on the 80486s memory bus design. When the Pentium processor started to gain mass acceptance, circa 1995, there were major differences in its bus design, and the VESA bus was not easily adaptable. This also made moving the bus to non-Intel architectures nearly impossible. Few Pentium motherboards with VESA slots were ever made. Limited number of slots available. Most PCs that used VESA Local Bus had only one or two slots available, as opposed to 5 or 6 ISA slots. This was because, as a direct branch of the 80486 memory bus, the VESA Local Bus didnt have the electrical ability to drive more than 1 or 2 (or 3 at the most) cards at a time.
Despite these problems, the VESA Local Bus was very commonplace on 486 motherboards. Probably a majority of 486-based systems had a VESA Local Bus video card, although early 486 systems never had VESA slots, as VESA debuted years after the introduction of the 486 processor.
|A39||BE0#||Byte Enable 0|
|A41||BE1#||Byte Enable 1|
|A42||BE2#||Byte Enable 2|
|A44||BE3#||Byte Enable 3|
|A58||LEADS#||Local Enable Address Strobe|
|B58||LBS16#||Local Bus Size 16|
This section is currently based solely on the work by Mark Sokos.
This file is intended to provide a basic functional overview of the Vesa Local Bus, so that hobbyists and amateurs can design their own VLB compatible cards.
It is not intended to provide complete coverage of the VLB standard.
VLB Connectors are usually inline with ISA connectors, so that adapter cards may use both. However, the VLB is separate, and does not need to connect to the ISA portion of the bus.
The 64 bit expansion of the bus (optional) does not add additional pins or connectors. Instead, it multiplexes the existing pins. The 32 bit VLB bus does not use the 64 bit signals shown in the above pinouts.
Byte Enable. Indicates that the 8 data lines corresponding to each signal will deliver valid data.
Burst Last. Indicates a VLB Burst Cycle, which will complete with *BRDY. The VLB Burst cycle consists of an address phase followed by four data phases.
Burst Ready. Indicates the end of the current burst transfer.
Data Bus. Valid bytes are indicated by *BE(x) signals.
Data/Command. Used with M/IO and W/R to indicate the type of cycle.
|ID2 Indicates wait:||0 = 1 wait cycle (min)|
|1 = no wait|
|ID3 Indicates bus speed:||0 = greater than 33.3 MHz|
|1 = less than 33.3 MHz|
Interrupt Request. Connected to IRQ9 on ISA bus. This allows standalone VLB adapters (not connected to ISA portion of the bus) to have one IRQ.
Local Enable Address Strobe. Set low by VLB master (not CPU). Also used for cache invalidation signal.
Local Bus Size 16. Used by slave device to indicate that it has a transfer width of only 16 bits.
Local Clock. Runs at the same frequency as the cpu, up to 50 MHz. 66 MHz is allowed for on-board devices.
Local Device: When appropriate address and M/IO signals are present on the bus, the VLB device must pull this line low to indicate that it is a VLB device. The VLB controller will then use the VLB bus for the transfer.
Local Ready. Indicates that the VLB device has completed the cycle. This signal is only used for single cycle transfers. *BRDY is used for burst transfers.
Local Grant. Indicates that an *LREQ signal has been granted, and control is being transferred to the new VLB master.
Local Request. Used by VLB Master to gain control of the bus.
Memory/IO. See D/C for signal description.
Ready Return. Indicates VLB cycle has been completed. May precede LRDY by one cycle.
Reset. Resets all VLB devices.
64-bit Expansion Signals
Acknowledge 64 bit transfer. Indicates that the device can perform the requested 64 bit transfer cycle.
Byte Enable. Indicates which bytes are valid (similar to BE0-BE3).
Upper 32 bits of data bus. Multiplexed with address bus.
Local Bus Size 64 bits. Used by VLB Master to indicate that it desires a 64 bit transfer.
Write/Read. See D/C for signal description.
64 Bit Data Transfer Timing Diagram:
Address Data Phase Phase _______ _______ _______ LCLK ___| |_______| |_______| |_______ ____ ______________________________________ *ADS |_______| _______________ _______________ A2-A31 ----<_______________><_______________>------------- D34-D63 Address Data D34-D63 _______________ _______________ D/C ----<_______________><_______________>------------- M/IO, W/R M/IO, W/R Data D32-33 _____ _____________________________ *LDEV |_______________| _____ _____________________________ *LBS64 |_______________| ______ _____________________________ *ACK64 |______________| _______________ D0-D31 --------------------<_______________>------------- _____________________ _____________ LRDY |______________|