Parallel interfaces
Pin Return Dir Description Active State
CC EE <-- Ready High
Y AA <-- On Line High
E C <-- Demand High
j m --> Data Strobe High
B D --> Data 1 n/a
F J --> Data 2 n/a
L N --> Data 3 n/a
R T --> Data 4 n/a
V X --> Data 5 n/a
Z b --> Data 6 n/a
n k --> Data 7 n/a
u w --> Data 8 n/a
z BB --> Parity n/a
d f <-- Ident 0 n/a
a c <-- Ident 1 n/a
v x --> Interface Verify Low
HH K --> +5 VDC (Test) High
r t <-- Parity Error High
M P <-- Bottom of Form High
S U <-- Top of Form High
p s --> Paper Instruction High
A H --> Buffer Clear High
W Y <-- Paper Moving High
FF DD <-- Paper Moving High
e h <-- Not VFU High
50 pin M/50 male connector layout
50 pin M/50 male connector
50 pin M/50 female connector layout
50 pin M/50 female connector
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Source(s) of this and additional information: Hardware Book
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