Parallel interfaces pinouts
Pin Return Dir Description Active State
22 6 <-- Ready High
21 5 <-- On Line High
23 7 <-- Demand High
38 37 --> Data Strobe High
19 3 --> Data 1 n/a
20 4 --> Data 2 n/a
1 2 --> Data 3 n/a
41 40 --> Data 4 n/a
34 18 --> Data 5 n/a
43 42 --> Data 6 n/a
36 35 --> Data 7 n/a
28 44 --> Data 8 n/a
29 13 --> Parity n/a
50 32 <-- Ident 0 n/a
49 16 <-- Ident 1 n/a
46 45 --> Interface Verify. Tied together. Low?
12 39 --> +5 VDC (Test) High
27 11 <-- Parity Error High
25 9 <-- Bottom of Form High
24 8 <-- Top of Form High
30 14 --> Paper Instruction High
31 15 --> Buffer Clear High
26 10 <-- Paper Moving High
48 17 <-- Paper Moving High
47 33 <-- Not VFU High
50 pin D-SUB male connector layout
50 pin D-SUB male connector
50 pin D-SUB female connector layout
50 pin D-SUB female connector
There are no any reports for this pinout! You may rate this document by clicking the button below.

Is this pinout
Source(s) of this and additional information: Hardware Book
This page contain parts under Copyright © 2000-2015 by pinouts.ru team.
No portion of this webpage may be reproduced in any form without providing visible HTML link to Old.Pinouts.ru . Webmaster permission required in any other cases.
Efforts have been made to ensure this page is correct, but it is the responsibility of the user to verify the data is correct for their application.