Motherboard connectors pinouts  > obsolete computers pinouts
Pin Name Description
1GNDGround
2GNDGround
3VCC+5 VDC
4VCC+5 VDC
5/CFGOUTConfigout AutoConfig signal (not connected)
6/CFGINConfigin AutoConfig signal (grounded)
7GNDGround
8CCKQ3.58 MHz CCKQ clock (C3)
9CDAC7.16 MHz CDAC clock (90? before system clock)
10CCK3.58 MHz CCK clock (C1)
11/OVROverride (Disables /DTACK generation of Gary)
12XRDYExternal Ready (Generates wait states while low).
13/INT2Level 2 Interrupt
14n/cnot connected
15A5Address Bus 5
16/INT6Level 6 Interrupt
17A6Address Bus 6
18A4Address Bus 4
19GNDGround
20A3Address Bus 3
21A2Address Bus 2
22A7Address Bus 7
23A1Address Bus 1
24A8Address Bus 8
25/FC0Processor Function Code Status (bit 0)
26A9Address Bus 9
27/FC1Processor Function Code Status (bit 1)
28A10Address Bus 10
29/FC2Processor Function Code Status (bit 2)
30A11Address Bus 11
31GNDGround
32A12Address Bus 12
33A13Address Bus 13
34/IPL0Interrupt Priority Level (bit 0)
35A14Address Bus 14
36/IPL1Interrupt Priority Level (bit 1)
37A15Address Bus 15
38/IPL2Interrupt Priority Level (bit 2)
39A16Address Bus 16
40/BERRBus Error
41A17Address Bus 17
42/VPAValid Peripheral Address (asserted by Gary)
43GNDGround
44EE Clock
45/VMAValid Memory Address (asserted by Gary)
46A18Address Bus 18
47/RSTReset
48A19Address Bus 19
49/HLTHalt
50A20Address Bus 20
51A22Address Bus 22
52A21Address Bus 21
53A23Address Bus 23
54/BRBus Request
55GNDGround
56/BGACKBus Grant Acknowledge
57D15Data Bus 15
58/BGBus Grant
59D14Data Bus 14
60/DTACKData Transfer Acknowledge (normally asserted by Gary)
61D13Data Bus 13
62R/WRead/Write (high=read, low=write)
63D12Data Bus 12
64/LDSLower Data Strobe
65D11Data Bus 11
66/UDSUpper Data Strobe
67GNDGround
68/ASAddress Strobe
69D0Data Bus 0
70D10Data Bus 10
71D1Data Bus 1
72D9Data Bus 9
73D2Data Bus 2
74D8Data Bus 8
75D3Data Bus 3
76D7Data Bus 7
77D4Data Bus 4
78D6Data Bus 6
79GNDGround
80D5Data Bus 5

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Source(s) of this and additional information: Darren Ewaniuk"s CDTV Technical Information, from Hardware Book
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