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172 pin MCA bus connector layout
172 pin MCA bus connector
plus MCA memory-matched extensions, MCA AVEC Auxiliary Video Extension Connector

Micro Channel architecture (in practice almost always shortened to MCA) was a proprietary 16 or 32-bit parallel computer bus created by IBM in the 1980s for use on their new PS/2 computers. For a time MCA could be found in the PS/2, RS/6000, AS/400 and even some of the System/370 mainframes. However all of these later moved on to more capable, standards based, busses (such as PCI) and MCA is no longer used.

MCA was primarily a 32-bit bus, but the system also supported a 16-bit mode which was primarily to lower the cost of connectors and logic in Intel-based machines like the PS/2. The situation was never that simple however, as both the 32-bit and 16-bit versions had a number of additional optional connectors which resulted in a huge number of physically incompatible cards. On the upside, MCA also moved the pins around to minimize interference, a ground or a supply was located within 3 pins of every signal.

The data rate was increased from ISAs 8MHz to 10, for a small improvement in performance. However the communications was now driven by the bus as opposed to the CPU, so real throughput was greatly increased, about four times, to 40MBps (of a theoretical 66). With bus-mastering the card could talk to each other directly so the performance was independent of the CPU. This led to possible collisions when more than one card would try to master, but MCA included an arbitration feature to correct for these situations, and also allowed a master to use a burst-mode where they had complete control for up to 12 milliseconds. Multiple busmaster support and improved arbitration means that several such devices can coexist and share the system bus. MCA busmasters can even use the bus to talk directly to each other at speeds faster than the system CPU, without any other system intervention. Arbitration enhancement also provides that we have better system throughput since control is passed more efficiently. Advanced interrupt handling refers to the use of level sensitive interrupts to handle system requests. Rather than a dedicated interrupt line, several lines can be shared to provide more possible interrupts. The final major improvement was POS, the Programmable Option Select, which allowed all setup to take place in software. This feature is taken for granted now, but at the time setup was a huge chore for ISA systems. POS was a simple system that included device IDs in firmware, which the drivers in the computer were supposed to interpret. This is the basis of plug-and-play today.

Although MCA was a huge improvement over ISA, it was limited only to IBM hardware. It was not compatible with either EISA or XT bus architecture so older cards cannot be used with it. This small market made for very high prices, and IBM didnt help matters by charging high licensing fees. MCA was largely ignored, and with the introduction of PCI, MCA swiftly disappeared.

Pin Signal Name Pin Signal Name
B04 14.3 MHz OSZ A04 A11
B05 GND A05 A10
B06 A23 A06 A09
B07 A22 A07 +5 Vdc
B08 A21 A08 A08
B09 GND A09 A07
B10 A20 A10 A06
B11 A19 A11 +5 Vdc
B12 A18 A12 A05
B13 GND A13 A04
B14 A17 A14 A03
B15 A16 A15 +5 Vdc
B16 A15 A16 A02
B17 GND A17 A01
B18 A14 A18 A00
B19 A13 A19 +12 Vdc
B20 A12 A20 -ADL
B22 -IRQ 09 A22 -BURST
B23 -IRQ 03 A23 -12 Vdc
B24 -IRQ 04 A24 ARB 00
B25 GND A25 -ARB 01
B26 -IRQ 05 A26 ARB 02
B27 -IRQ 06 A27 -12 Vdc
B28 -IRQ 07 A28 ARB 03
B31 DPAR(0) A31 +5 Vdc
B32 -CHCK A32 -SO
B33 GND A33 -S1
B34 -CMD A34 M/-IO
B35 CHRDYRTN A35 +12 Vdc
B37 GND A37 D 0
B38 D 01 A38 D 02
B39 D 03 A39 +5 Vdc
B40 D 04 A40 D 05
B41 GND A41 D 06
B42 CHRESET A42 D 07
B44 -SDR (0) A44 -DS 16 RTN
B46 - key - A46 - key -
B47 - key - A47 - key -
B48 D 08 A48 +5 Vdc
B49 D 09 A49 D 10
B50 GND A50 D 11
B51 D 12 A51 D 13
B52 D 14 A52 +12 Vdc
B53 D 15 A53 DPAR(1)
B55 -IRQ 10 A55 -CD DS 16
B56 -IRQ 11 A56 +5 Vdc
B57 -IRQ 12 A57 -IRQ 14
B58 GND A58 -IRQ 15
B59 reserved A59 reserved
B60 reserved A60 reserved
Pin 32-bit bus
Signal Name
Pin 32-bit bus
Signal Name
B61 -SDR(1) A61 GND
B62 -MSDR A62 reserved
B63 GND A63 reserved
B64 D 16 A64 -SFDBKRTN
B65 D 17 A65 +12 Vdc
B66 D 18 A66 D 19
B67 GND A67 D 20
B68 D 22 A68 D 21
B69 D 23 A69 +5 Vdc
B70 DPAR(2) A70 D 24
B71 GND A71 D 25
B72 D 27 A72 D 26
B73 D 28 A73 +5 Vdc
B74 D 29 A74 D 30
B75 GND A75 D 31
B76 -BE 0 A76 DPAR(3)
B77 -BE 1 A77 +12 Vdc
B78 -BE 2 A78 -BE 3
B79 GND A79 -DS 32 RTN
B80 TR 32 A80 -CD DS 32
B81 A 24 A81 +5 Vdc
B82 A 25 A82 A 26
B83 GND A83 A 27
B84 A 29 A84 A 28
B85 A 30 A85 +5 Vdc
B86 A 31 A86 -APAREN
B87 GND A87 -APAR(0)
B88 APAR(2) A88 -APAR(1)
B89 APAR(3) A89 GND

MCA memory-matched extensions - pin AM1-BM1 / pin AM4-BM4

Pin Signal Name Pin Signal Name
BM4 Ground AM4 Reserved
BM3 Reserved AM3 -MMC_CMD
BM2 -MMCR AM2 Ground
BM1 Reserved AM1 -MMC

MCA AVEC Auxiliary Video Extension Connector - pin BV1-AV1 / pin BV10-BV10

Pin Signal Name Pin Signal Name
BV9 Ground AV9 HSYNC
BV7 P4 AV7 Ground
BV6 P3 AV6 P6
BV5 Ground AV5 EDCLK
BV3 P1 AV3 Ground
BV2 P0 AV2 P7
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Source(s) of this and additional information:, Micro Channel architecture
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