49 47 45 5 3 1 +---------//-----+ | H H H //H H H | | ======//====== | | H H H// H H H | +-----//---------+ 50 48 46 6 4 2
Pin | Name | Dir | Description |
---|---|---|---|
1 | /CS1 | Memory Read in addresses 4000~7FFF | |
2 | /CS2 | Memory Read in addresses 8000~BFFF | |
3 | /CS12 | Memory Read in addresses 4000~BFFF | |
4 | /SLTSL | Low when Slot 2 (cartridge slot) is selected | |
5 | N/C | N/A | Not Connected. |
6 | /RFSH | Refresh signal from CPU | |
7 | /WAIT | OC, Tells CPU to wait. Refresh signal is not maintained | |
8 | /INT | OC, Requests a interrupt to CPU (call to addr 38h) | |
9 | /M1 | CPU fetches first part of instruction from memory. | |
10 | /BUSDIR | NC, was used to control the data direction. | |
11 | /IORQ | I/O request signal. (Address=Port) | |
12 | /MREQ | Memory request signal. (Address=Address) | |
13 | /WR | Write signal (strobe) | |
14 | /RD | Read signal (strobe) | |
15 | /RESET | Reset | |
16 | n/c | - | Not connected. |
17 | A9 | Address 9 | |
18 | A15 | Address 15 | |
19 | A11 | Address 11 | |
20 | A10 | Address 10 | |
21 | A7 | Address 7 | |
22 | A6 | Address 6 | |
23 | A12 | Address 12 | |
24 | A8 | Address 8 | |
25 | A14 | Address 14 | |
26 | A13 | Address 13 | |
27 | A1 | Address 1 | |
28 | A0 | Address 0 | |
29 | A3 | Address 3 | |
30 | A2 | Address 2 | |
31 | A5 | Address 5 | |
32 | A4 | Address 4 | |
33 | D1 | Data 1 | |
34 | D0 | Data 0 | |
35 | D3 | Data 3 | |
36 | D2 | Data 2 | |
37 | D5 | Data 5 | |
38 | D4 | Data 4 | |
39 | D7 | Data 7 | |
40 | D6 | Data 6 | |
41 | GND | Ground | |
42 | CLOCK | CPU clock,
|
|
43 | GND | Ground | |
44 | SW1 | - | Insert/remove detection for protection |
45 | +5V | +5 VDC (300mA max/Slot) | |
46 | SW2 | - | Insert/remove detection for protection |
47 | +5V | +5 VDC (300mA max/Slot) | |
48 | +12V | +12 VDC (50mA max/Slot) | |
49 | SOUNDIN | Sound input (-5dBm) | |
50 | -12V | -12 VDC (50mA max/Slot) |
Note: Direction is Computer relative Peripheral.