50 PIN UNKNOWN CONNECTOR
| Pin | Name | Description |
|---|---|---|
| 1 | +5V | +5 VDC |
| 2 | A1 | Address bit 1 |
| 3 | A2 | Address bit 2 |
| 4 | A3 | Address bit 3 |
| 5 | A4 | Address bit 4 |
| 6 | A5 | Address bit 5 |
| 7 | A6 | Address bit 6 |
| 8 | A7 | Address bit 7 |
| 9 | A8 | Address bit 8 |
| 10 | A9 | Address bit 9 |
| 11 | A10 | Address bit 10 |
| 12 | A11 | Address bit 11 |
| 13 | A12 | Address bit 12 |
| 14 | A13 | Address bit 13 |
| 15 | A14 | Address bit 14 |
| 16 | A15 | Address bit 15 |
| 17 | A16 | Address bit 16 |
| 18 | A17 | Address bit 17 |
| 19 | A18 | Address bit 18 |
| 20 | A19 | Address bit 19 |
| 21 | A20 | Address bit 20 |
| 22 | A21 | Address bit 21 |
| 23 | A22 | Address bit 22 |
| 24 | A23 | Address bit 23 |
| 25 | GND | Ground |
| 26 | GND | Ground |
| 27 | /DTACK | Data Transfer Acknowledge |
| 28 | /AS | Address Strobe |
| 29 | /ROM_CS | ROM Chip Select |
| 30 | 16M | 16 MHz Clock |
| 31 | /EXT_DTACK | External Data Transfer Acknowledge |
| 32 | /DELAY_CS | |
| 33 | D0 | Data bit 0 |
| 34 | D1 | Data bit 1 |
| 35 | D2 | Data bit 2 |
| 36 | D3 | Data bit 3 |
| 37 | D4 | Data bit 4 |
| 38 | D5 | Data bit 5 |
| 39 | D6 | Data bit 6 |
| 40 | D7 | Data bit 7 |
| 41 | D8 | Data bit 8 |
| 42 | D9 | Data bit 9 |
| 43 | D10 | Data bit 10 |
| 44 | D11 | Data bit 11 |
| 45 | D12 | Data bit 12 |
| 46 | D13 | Data bit 13 |
| 47 | D14 | Data bit 14 |
| 48 | D15 | Data bit 15 |
| 49 | +5V | +5 VDC |
| 50 | +5V | +5 VDC |
D0-D15
Unbuffered data bus, bits 0 through 15
A1-A23
Unbuffered 68HC000 address bus, bits 1 through 23
16M
16 MHz system clock
/EXT.DTACK
External data transfer acknowledge that disables main system /DTACK.
/AS
68HC000 Address strobe
/DTACK
Data transfer acknowledge, /DTACK input to 68HC000.
/DELAY_CS
This signal is generated by the addressing PAL and is used to put the ROM board into the idle mode by inserting multiple wait states.
/ROM_CS
Permanent ROM chip select signal. Selects in range $90 0000 through $9F FFFF.
correct
incorrect